1. Field of the Invention
This invention relates to a semiconductor memory device, more particularly, to a static random access memory (SRAM) device or a dynamic random access memory (DRAM) device with a bit-compression test mode function to reduce a test time thereof.
2. Description of the Related Art
Conventionally, a typical SRAM or DRAM device includes a data compression circuit for the purpose of reducing the test time thereof. Such a data compression circuit carries out a comparison between each data bit read from corresponding memory cells, in a test mode, and compresses and outputs the result of the comparison. In this case, the respective data bits to be fed to the data compression circuit in the test mode have the same logic level as each other, and are read from a plurality of memory cells connected to a corresponding word line, based on a word line activation signal, for driving the word line, which is generated by decoding an address signal.
For example, referring to the constitution shown in FIG. 3 which is not a prior art, a data compression circuit indicated by reference 17 carries out a comparison between each bit data D.sub.1, D.sub.2, D.sub.3, . . . , read from corresponding memory cells in the test mode, and compresses a result of the comparison to thereby output a logic judgement result at node N thereof. In this case, a signal appearing at node N when the respective bit data D.sub.1, D.sub.2, D.sub.3, . . . , coincide with each other (i.e., when each bit data is at the same logic level), and a signal appearing at node N when the respective bit data do not coincide with each other, exhibit logic levels different from each other.
When the memory functions normally, and where a word line activation signal is generated for driving a corresponding word line, respective data bits fed to the data compression circuit in the test mode, i.e., each data bit read from memory cells connected to an identical word line, have the same logic level as each other, as stated above. Accordingly, the logic judgement result of the data compression circuit indicates "coincidence". In this case, by outputting the logic judgement result indicating the coincidence to the outside of the memory device, it is possible to recognize that the memory can carry out a normal operation.
On the other hand, where there are some defects present in memory cells connected to an identical word line, and when a corresponding word line activation signal is generated, each data bit read from the memory cells connected to the word line in the test mode cannot have the same logic level as each other. Accordingly, the logic judgement result of the data compression circuit indicates "non-coincidence". In this case, based on the logic judgement result indicating non-coincidence, it is possible to recognize that the memory cannot carry out a normal operation.
In the prior art, however, where a word line activation signal is not generated due to some defect or erroneous operation of the peripheral circuits in the test mode, a problem occurs in that, although the memory does not carry out a normal operation, respective data bits read from memory cells connected to an identical word line coincide in level with each other, and accordingly, a logic judgement result of the data compression circuit indicates "coincidence".
Thus, the prior art poses problem in that, based on the logic judgement result indicating the "coincidence" generated by the memory device, an erroneous recognition that the memory can carry out a normal operation is made.